libTriton version 1.0 build 1590
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ARM32 SMT semantics supported

[internal] List of the supported semantics for the ARM32 architecture.

Mnemonic Description
ADC Add with Carry
ADD Add
ADDW Add
ADR Form PC-relative address
AND Bitwise AND
ASR Arithmetic Shift Right
B Branch
BFC Bitfield Clear
BFI Bitfield Insert
BIC Bitwise Bit Clear
BL Branch with Link
BLX Branch with Link and Exchange
BX Branch and Exchange
CBNZ Compare and Branch on Nonzero
CBZ Compare and Branch on Zero
CLZ Count Leading Zeros
CMN Compare Negative
CMP Compare
EOR Bitwise Exclusive OR
IT If-Then
LDM Load Multiple Registers
LDR Load Register
LDRB Load Register Byte
LDRD Load Register Dual
LDREX Load Register Exclusive
LDRH Load Register Halfword
LDRSB Load Register Signed Byte
LDRSH Load Register Signed Halfword
LSL Logical Shift Left
LSR Logical Shift Right
MLA Multiply Accumulate
MLS Multiply and Subtract
MOV Move Register
MOVT Move Top
MOVW Move Register
MUL Multiply
MVN Bitwise NOT
NOP No Operation
ORN Bitwise OR
ORR Bitwise OR
POP Pop Multiple Registers
PUSH Push Multiple Registers
RBIT Reverse Bits
REV Byte-Reverse Word
REV16 Reverse bytes in 16-bit halfwords
ROR Rotate Right
RRX Rotate Right with Extend
RSB Reverse Subtract
RSC Reverse Subtract with Carry
SBC Subtract with Carry
SBFX Signed Bitfield Extract
SDIV Signed Divide
SMLABB Signed Multiply Accumulate
SMLABT Signed Multiply Accumulate
SMLATB Signed Multiply Accumulate
SMLATT Signed Multiply Accumulate
SMULL Signed Multiply Long
STM Store Multiple Registers
STMIB Store Multiple Increment Before
STR Store Register
STRB Store Register Byte
STRD Store Register Dual
STREX Store Register Exclusive
STRH Store Register Halfword
SUB Substract
SUBW Substract
SXTB Signed Extend Byte
SXTH Sign Extend Halfword
TBB Table Branch Byte
TBH Table Branch Halfword
TEQ Test Equivalence
TST Test
UBFX Unsigned Bitfield Extract
UDIV Unsigned Divide
UMULL Unsigned Multiply Long
UXTB Unsigned Extend Byte
UXTH Unsigned Extend Halfword