8#ifndef TRITON_ARCHENUMS_HPP
9#define TRITON_ARCHENUMS_HPP
67 #define REG_SPEC(UPPER_NAME, _1, _2, _3, _4, _5, _6, _7, _8) \
68 ID_REG_X86_##UPPER_NAME,
69 #define REG_SPEC_NO_CAPSTONE REG_SPEC
70 #include "triton/x86.spec"
72 #define REG_SPEC(UPPER_NAME, _1, _2, _3, _4, _5) \
73 ID_REG_AARCH64_##UPPER_NAME,
74 #define REG_SPEC_NO_CAPSTONE REG_SPEC
75 #define SYS_REG_SPEC REG_SPEC
76 #include "triton/aarch64.spec"
78 #define REG_SPEC(UPPER_NAME, _1, _2, _3, _4, _5) \
79 ID_REG_ARM32_##UPPER_NAME,
80 #define REG_SPEC_NO_CAPSTONE REG_SPEC
81 #include "triton/arm32.spec"
197 template <>
struct hash<
triton::arch::register_e> :
public hash<uint64_t> {
register_e
Types of register.
@ ID_REG_INVALID
invalid = 0
@ ID_REG_LAST_ITEM
must be the last item
vas_e
Vector arrangement specifier.
condition_e
Types of condition.
@ ID_SHIFT_LSR
Logical Shift Right (immediate)
@ ID_SHIFT_LSR_REG
Logical Shift Right (register)
@ ID_SHIFT_ASR
Arithmetic Shift Right (immediate)
@ ID_SHIFT_ROR_REG
Rotate Right (register)
@ ID_SHIFT_ROR
Rotate Right (immediate)
@ ID_SHIFT_ASR_REG
Arithmetic Shift Right (register)
@ ID_SHIFT_RRX
Rotate Right with Extend (immediate)
@ ID_SHIFT_RRX_REG
Rotate Right with Extend (register)
@ ID_SHIFT_LAST_ITEM
Must be the last item.
@ ID_SHIFT_LSL_REG
Logical Shift Left (register)
@ ID_SHIFT_INVALID
invalid
@ ID_SHIFT_LSL
Logical Shift Left (immediate)
@ ID_VAS_4S
4 lanes, each containing a 32-bit element.
@ ID_VAS_2D
2 lanes, each containing a 64-bit element.
@ ID_VAS_1D
1 lane containing a 64-bit element.
@ ID_VAS_16B
16 lanes, each containing an 8-bit element.
@ ID_VAS_8B
8 lanes, each containing an 8-bit element.
@ ID_VAS_8H
8 lanes, each containing a 16-bit element.
@ ID_VAS_4H
4 lanes, each containing a 16-bit element.
@ ID_VAS_LAST_ITEM
must be the last item.
@ ID_VAS_2S
2 lanes, each containing a 32-bit element.
@ ID_EXTEND_SXTW
Extracts a word (32-bit) value from a register and zero extends it to the size of the register.
@ ID_EXTEND_UXTX
Use the whole 64-bit register.
@ ID_EXTEND_SXTX
Use the whole 64-bit register.
@ ID_EXTEND_SXTH
Extracts a halfword (16-bit) value from a register and zero extends it to the size of the register.
@ ID_EXTEND_UXTB
Extracts a byte (8-bit) value from a register and zero extends it to the size of the register.
@ ID_EXTEND_INVALID
invalid
@ ID_EXTEND_UXTW
Extracts a word (32-bit) value from a register and zero extends it to the size of the register.
@ ID_EXTEND_SXTB
Extracts a byte (8-bit) value from a register and zero extends it to the size of the register.
@ ID_EXTEND_UXTH
Extracts a halfword (16-bit) value from a register and zero extends it to the size of the register.
@ ID_EXTEND_LAST_ITEM
Must be the last item.
@ ID_CONDITION_HS
Higher or same (unsigned >=). C set.
@ ID_CONDITION_PL
Positive or zero. N clear.
@ ID_CONDITION_VC
No overflow. V clear.
@ ID_CONDITION_LE
Signed <=. Z set, N and V differ.
@ ID_CONDITION_VS
Overflow. V set.
@ ID_CONDITION_LAST_ITEM
must be the last item.
@ ID_CONDITION_MI
Negative. N set.
@ ID_CONDITION_GE
Signed >=. N and V the same.
@ ID_CONDITION_GT
Signed >. Z clear, N and V the same.
@ ID_CONDITION_HI
Higher (unsigned >). C set and Z clear.
@ ID_CONDITION_NE
Not equal. Z clear.
@ ID_CONDITION_AL
Always. Any flags. This suffix is normally omitted.
@ ID_CONDITION_LO
Lower (unsigned <). C clear.
@ ID_CONDITION_LT
Signed <. N and V differ.
@ ID_CONDITION_LS
Lower or same (unsigned <=). C clear or Z set.
@ ID_CONDITION_INVALID
invalid
@ ID_CONDITION_EQ
Equal. Z set.
@ ID_PREFIX_INVALID
invalid
@ ID_PREFIX_LAST_ITEM
must be the last item