libTriton  version 0.9 build 1502
instruction.cpp
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1 /*
3 ** Copyright (C) - Triton
4 **
5 ** This program is under the terms of the Apache License 2.0.
6 */
7 
8 #include <cstring>
9 
10 #include <triton/exceptions.hpp>
11 #include <triton/immediate.hpp>
12 #include <triton/instruction.hpp>
13 
14 
15 
16 namespace triton {
17  namespace arch {
18 
20  this->address = 0;
21  this->branch = false;
23  this->conditionTaken = 0;
24  this->controlFlow = false;
26  this->size = 0;
27  this->tainted = false;
28  this->thumb = false;
29  this->tid = 0;
30  this->type = 0;
31  this->updateFlag = false;
32  this->writeBack = false;
33 
34  std::memset(this->opcode, 0x00, sizeof(this->opcode));
35  }
36 
37 
39  this->setOpcode(opcode, opSize);
40  }
41 
42 
44  this->setAddress(addr);
45  }
46 
47 
49  this->copy(other);
50  }
51 
52 
54  /* See #828: Release ownership before calling container destructor */
55  this->loadAccess.clear();
56  this->readImmediates.clear();
57  this->readRegisters.clear();
58  this->storeAccess.clear();
59  this->symbolicExpressions.clear();
60  this->writtenRegisters.clear();
61  }
62 
63 
65  this->copy(other);
66  return *this;
67  }
68 
69 
70  void Instruction::copy(const Instruction& other) {
71  this->address = other.address;
72  this->branch = other.branch;
73  this->codeCondition = other.codeCondition;
74  this->conditionTaken = other.conditionTaken;
75  this->controlFlow = other.controlFlow;
76  this->loadAccess = other.loadAccess;
77  this->operands = other.operands;
78  this->prefix = other.prefix;
79  this->readImmediates = other.readImmediates;
80  this->readRegisters = other.readRegisters;
81  this->size = other.size;
82  this->storeAccess = other.storeAccess;
84  this->tainted = other.tainted;
85  this->tid = other.tid;
86  this->type = other.type;
88  this->updateFlag = other.updateFlag;
89  this->writeBack = other.writeBack;
90  this->writtenRegisters = other.writtenRegisters;
91 
92  std::memcpy(this->opcode, other.opcode, sizeof(this->opcode));
93 
94  this->disassembly.clear();
95  this->disassembly.str(other.disassembly.str());
96  }
97 
98 
100  return this->tid;
101  }
102 
103 
105  this->tid = tid;
106  }
107 
108 
110  return this->address;
111  }
112 
113 
115  return this->address + this->size;
116  }
117 
118 
120  this->address = addr;
121  }
122 
123 
124  std::string Instruction::getDisassembly(void) const {
125  return this->disassembly.str();
126  }
127 
128 
130  return this->opcode;
131  }
132 
133 
135  if (size >= sizeof(this->opcode))
136  throw triton::exceptions::Instruction("Instruction::setOpcode(): Invalid size (too big).");
137  std::memcpy(this->opcode, opcode, size);
138  this->size = size;
139  }
140 
141 
143  return this->size;
144  }
145 
146 
148  return this->type;
149  }
150 
151 
153  return this->prefix;
154  }
155 
156 
158  return this->codeCondition;
159  }
160 
161 
162  std::set<std::pair<triton::arch::MemoryAccess, triton::ast::SharedAbstractNode>>& Instruction::getLoadAccess(void) {
163  return this->loadAccess;
164  }
165 
166 
167  std::set<std::pair<triton::arch::MemoryAccess, triton::ast::SharedAbstractNode>>& Instruction::getStoreAccess(void) {
168  return this->storeAccess;
169  }
170 
171 
172  std::set<std::pair<triton::arch::Register, triton::ast::SharedAbstractNode>>& Instruction::getReadRegisters(void) {
173  return this->readRegisters;
174  }
175 
176 
177  std::set<std::pair<triton::arch::Register, triton::ast::SharedAbstractNode>>& Instruction::getWrittenRegisters(void) {
178  return this->writtenRegisters;
179  }
180 
181 
182  std::set<std::pair<triton::arch::Immediate, triton::ast::SharedAbstractNode>>& Instruction::getReadImmediates(void) {
183  return this->readImmediates;
184  }
185 
186 
187  std::set<triton::arch::Register>& Instruction::getUndefinedRegisters(void) {
188  return this->undefinedRegisters;
189  }
190 
191 
193  this->loadAccess.insert(std::make_pair(mem, node));
194  }
195 
196 
198  auto it = this->loadAccess.begin();
199 
200  while (it != this->loadAccess.end()) {
201  if (it->first.getAddress() == mem.getAddress())
202  it = this->loadAccess.erase(it);
203  else
204  ++it;
205  }
206  }
207 
208 
210  this->storeAccess.insert(std::make_pair(mem, node));
211  }
212 
213 
215  auto it = this->storeAccess.begin();
216 
217  while (it != this->storeAccess.end()) {
218  if (it->first.getAddress() == mem.getAddress())
219  it = this->storeAccess.erase(it);
220  else
221  ++it;
222  }
223  }
224 
225 
227  this->readRegisters.insert(std::make_pair(reg, node));
228  }
229 
230 
232  auto it = this->readRegisters.begin();
233 
234  while (it != this->readRegisters.end()) {
235  if (it->first.getId() == reg.getId())
236  it = this->readRegisters.erase(it);
237  else
238  ++it;
239  }
240  }
241 
242 
244  this->writtenRegisters.insert(std::make_pair(reg, node));
245  }
246 
247 
249  auto it = this->writtenRegisters.begin();
250 
251  while (it != this->writtenRegisters.end()) {
252  if (it->first.getId() == reg.getId())
253  it = this->writtenRegisters.erase(it);
254  else
255  ++it;
256  }
257  }
258 
259 
261  this->readImmediates.insert(std::make_pair(imm, node));
262  }
263 
264 
266  auto it = this->readImmediates.begin();
267 
268  while (it != this->readImmediates.end()) {
269  if (it->first.getValue() == imm.getValue())
270  it = this->readImmediates.erase(it);
271  else
272  ++it;
273  }
274  }
275 
276 
278  this->undefinedRegisters.insert(reg);
279  }
280 
281 
283  this->undefinedRegisters.erase(reg);
284  }
285 
286 
288  this->size = size;
289  }
290 
291 
293  this->type = type;
294  }
295 
296 
298  this->prefix = prefix;
299  }
300 
301 
302  void Instruction::setWriteBack(bool state) {
303  this->writeBack = state;
304  }
305 
306 
307  void Instruction::setUpdateFlag(bool state) {
308  this->updateFlag = state;
309  }
310 
311 
313  this->codeCondition = codeCondition;
314  }
315 
316 
317  void Instruction::setThumb(bool state) {
318  this->thumb = state;
319  }
320 
321 
322  void Instruction::setDisassembly(const std::string& str) {
323  this->disassembly.clear();
324  this->disassembly.str(str);
325  }
326 
327 
328  void Instruction::setTaint(bool state) {
329  this->tainted = state;
330  }
331 
332 
334  for (auto it = this->symbolicExpressions.begin(); it != this->symbolicExpressions.end(); it++) {
335  if ((*it)->isTainted == true) {
336  this->tainted = true;
337  break;
338  }
339  }
340  }
341 
342 
344  if (expr == nullptr)
345  throw triton::exceptions::Instruction("Instruction::addSymbolicExpression(): Cannot add a null expression.");
346  this->symbolicExpressions.push_back(expr);
347  return this->symbolicExpressions.back();
348  }
349 
350 
351  bool Instruction::isBranch(void) const {
352  return this->branch;
353  }
354 
355 
356  bool Instruction::isControlFlow(void) const {
357  return this->controlFlow;
358  }
359 
360 
361  bool Instruction::isConditionTaken(void) const {
362  return this->conditionTaken;
363  }
364 
365 
366  bool Instruction::isTainted(void) const {
367  return this->tainted;
368  }
369 
370 
371  bool Instruction::isSymbolized(void) const {
372  for (auto it = this->symbolicExpressions.begin(); it != this->symbolicExpressions.end(); it++) {
373  if ((*it)->isSymbolized() == true)
374  return true;
375  }
376  return false;
377  }
378 
379 
380  bool Instruction::isMemoryRead(void) const {
381  if (this->loadAccess.size() >= 1)
382  return true;
383  return false;
384  }
385 
386 
387  bool Instruction::isMemoryWrite(void) const {
388  if (this->storeAccess.size() >= 1)
389  return true;
390  return false;
391  }
392 
393 
395  switch(target.getType()) {
396 
398  for (auto&& pair : this->readImmediates) {
399  if (pair.first == target.getConstImmediate())
400  return true;
401  }
402  break;
403 
405  for (auto&& pair : this->loadAccess) {
406  const triton::arch::MemoryAccess& m1 = pair.first;
407  const triton::arch::MemoryAccess& m2 = target.getConstMemory();
408 
409  if (m1.isOverlapWith(m2))
410  return true;
411  }
412  break;
413 
415  for (auto&& pair : this->readRegisters) {
416  const triton::arch::Register& r1 = pair.first;
417  const triton::arch::Register& r2 = target.getConstRegister();
418 
419  if (r1.isOverlapWith(r2))
420  return true;
421  }
422  break;
423 
424  default:
425  throw triton::exceptions::Instruction("Instruction::isReadFrom(): Invalid type operand.");
426  }
427 
428  return false;
429  }
430 
431 
433  switch(target.getType()) {
434 
436  break;
437 
439  for (auto&& pair : this->storeAccess) {
440  const triton::arch::MemoryAccess& m1 = pair.first;
441  const triton::arch::MemoryAccess& m2 = target.getConstMemory();
442 
443  if (m1.isOverlapWith(m2))
444  return true;
445  }
446  break;
447 
449  for (auto&& pair : this->writtenRegisters) {
450  const triton::arch::Register& r1 = pair.first;
451  const triton::arch::Register& r2 = target.getConstRegister();
452 
453  if (r1.isOverlapWith(r2))
454  return true;
455  }
456  break;
457 
458  default:
459  throw triton::exceptions::Instruction("Instruction::isWriteTo(): Invalid type operand.");
460  }
461 
462  return false;
463  }
464 
465 
466  bool Instruction::isPrefixed(void) const {
468  return false;
469  return true;
470  }
471 
472 
473  bool Instruction::isWriteBack(void) const {
474  return this->writeBack;
475  }
476 
477 
478  bool Instruction::isUpdateFlag(void) const {
479  return this->updateFlag;
480  }
481 
482 
483  bool Instruction::isThumb(void) const {
484  return this->thumb;
485  }
486 
487 
489  this->branch = flag;
490  }
491 
492 
494  this->controlFlow = flag;
495  }
496 
497 
499  this->conditionTaken = flag;
500  }
501 
502 
503  void Instruction::clear(void) {
504  this->address = 0;
505  this->branch = false;
507  this->conditionTaken = 0;
508  this->controlFlow = false;
510  this->size = 0;
511  this->tainted = false;
512  this->tid = 0;
513  this->type = 0;
514  this->updateFlag = false;
515  this->writeBack = false;
516 
517  /* Clear the stringstream (See #975) */
518  std::stringstream().swap(this->disassembly);
519 
520  this->loadAccess.clear();
521  this->operands.clear();
522  this->readImmediates.clear();
523  this->readRegisters.clear();
524  this->storeAccess.clear();
525  this->symbolicExpressions.clear();
526  this->writtenRegisters.clear();
527 
528  std::memset(this->opcode, 0x00, sizeof(this->opcode));
529  }
530 
531 
532  std::ostream& operator<<(std::ostream& stream, const Instruction& inst) {
533  stream << "0x" << std::hex << inst.getAddress() << ": " << inst.getDisassembly() << std::dec;
534  return stream;
535  }
536 
537 
538  std::ostream& operator<<(std::ostream& stream, const Instruction* inst) {
539  stream << *inst;
540  return stream;
541  }
542 
543  };
544 };
This class is used to represent an immediate.
Definition: immediate.hpp:37
TRITON_EXPORT triton::uint64 getValue(void) const
Returns the value of the operand.
Definition: immediate.cpp:34
This class is used when to represent an instruction.
Definition: instruction.hpp:48
TRITON_EXPORT void setLoadAccess(const triton::arch::MemoryAccess &mem, const triton::ast::SharedAbstractNode &node)
Sets a load access.
TRITON_EXPORT std::set< std::pair< triton::arch::Register, triton::ast::SharedAbstractNode > > & getReadRegisters(void)
Returns the list of all implicit and explicit register (flags includes) inputs (read)
TRITON_EXPORT Instruction & operator=(const Instruction &other)
Copies an Instruction.
Definition: instruction.cpp:64
TRITON_EXPORT void setUpdateFlag(bool state)
Sets the updateFlag of the instruction.
TRITON_EXPORT triton::uint32 getSize(void) const
Returns the size of the instruction.
TRITON_EXPORT void setDisassembly(const std::string &str)
Sets the disassembly of the instruction.
std::set< std::pair< triton::arch::Immediate, triton::ast::SharedAbstractNode > > readImmediates
Implicit and explicit immediate inputs (read). This field is set at the semantics level.
Definition: instruction.hpp:87
triton::uint8 opcode[32]
The opcode of the instruction.
Definition: instruction.hpp:60
TRITON_EXPORT bool isWriteBack(void) const
Returns true if the instruction performs a write back. Mainly used for AArch64 instructions like LDR.
TRITON_EXPORT void removeLoadAccess(const triton::arch::MemoryAccess &mem)
Removes a load access.
TRITON_EXPORT void setThumb(bool state)
Sets the Thumb mode of the instruction.
TRITON_EXPORT void setConditionTaken(bool flag)
Sets flag to define if the condition is taken or not.
std::stringstream disassembly
The disassembly of the instruction. This field is set at the disassembly level.
Definition: instruction.hpp:57
TRITON_EXPORT bool isWriteTo(const triton::arch::OperandWrapper &target) const
Returns whether the instruction writes the specified operand.
TRITON_EXPORT void setWrittenRegister(const triton::arch::Register &reg, const triton::ast::SharedAbstractNode &node)
Sets a written register.
TRITON_EXPORT const triton::uint8 * getOpcode(void) const
Returns the opcode of the instruction.
triton::uint32 size
The size of the instruction.
Definition: instruction.hpp:63
triton::arch::x86::prefix_e prefix
The prefix of the instruction. This field is set at the disassembly level. Mainly used for X86.
Definition: instruction.hpp:69
bool thumb
True if this is a Thumb instruction. (Note that isThumb() in Arm32Cpu is used to determine the curren...
std::set< std::pair< triton::arch::MemoryAccess, triton::ast::SharedAbstractNode > > storeAccess
Implicit and explicit store access (write). This field is set at the semantics level.
Definition: instruction.hpp:78
triton::arch::arm::condition_e codeCondition
The code condition of the instruction. This field is set at the disassembly level....
Definition: instruction.hpp:72
TRITON_EXPORT bool isThumb(void) const
Returns true if it is a Thumb instruction.
TRITON_EXPORT std::set< std::pair< triton::arch::MemoryAccess, triton::ast::SharedAbstractNode > > & getStoreAccess(void)
Returns the list of all implicit and explicit store access.
TRITON_EXPORT void setType(triton::uint32 type)
Sets the type of the instruction.
TRITON_EXPORT void setPrefix(triton::arch::x86::prefix_e prefix)
Sets the prefix of the instruction (mainly for X86).
TRITON_EXPORT void setAddress(triton::uint64 addr)
Sets the address of the instruction.
TRITON_EXPORT std::set< std::pair< triton::arch::MemoryAccess, triton::ast::SharedAbstractNode > > & getLoadAccess(void)
Returns the list of all implicit and explicit load access.
TRITON_EXPORT void clear(void)
Clears all instruction information.
TRITON_EXPORT void setTaint(void)
Sets the taint of the instruction based on its expressions.
bool writeBack
True if this instruction performs a write back. Mainly used for AArch64 instruction like LDR.
TRITON_EXPORT void setStoreAccess(const triton::arch::MemoryAccess &mem, const triton::ast::SharedAbstractNode &node)
Sets a store access.
TRITON_EXPORT triton::uint32 getType(void) const
Returns the type of the instruction.
TRITON_EXPORT void removeReadRegister(const triton::arch::Register &reg)
Removes a read register.
TRITON_EXPORT bool isConditionTaken(void) const
Returns true if the condition is taken (e.g x86: jcc, cmovcc, setcc, ...).
TRITON_EXPORT bool isReadFrom(const triton::arch::OperandWrapper &target) const
Returns whether the instruction reads the specified operand.
TRITON_EXPORT bool isTainted(void) const
Returns true if at least one of its expressions is tainted.
std::set< std::pair< triton::arch::MemoryAccess, triton::ast::SharedAbstractNode > > loadAccess
Implicit and explicit load access (read). This field is set at the semantics level.
Definition: instruction.hpp:75
triton::uint32 type
The type of the instruction. This field is set at the disassembly level.
Definition: instruction.hpp:66
TRITON_EXPORT std::set< triton::arch::Register > & getUndefinedRegisters(void)
Returns the list of all implicit and explicit undefined registers.
TRITON_EXPORT void setWriteBack(bool state)
Sets the writeBack flag of the instruction.
TRITON_EXPORT triton::uint64 getAddress(void) const
Returns the address of the instruction.
TRITON_EXPORT bool isSymbolized(void) const
Returns true if at least one of its expressions contains a symbolic variable.
TRITON_EXPORT bool isMemoryRead(void) const
Returns true if the instruction contains an expression which reads the memory.
TRITON_EXPORT void removeUndefinedRegister(const triton::arch::Register &reg)
Removes an undefined register.
bool controlFlow
True if this instruction changes the control flow. This field is set at the disassembly level.
Definition: instruction.hpp:96
TRITON_EXPORT bool isMemoryWrite(void) const
Returns true if the instruction contains an expression which writes into the memory.
TRITON_EXPORT void setUndefinedRegister(const triton::arch::Register &reg)
Sets an undefined register.
TRITON_EXPORT triton::uint32 getThreadId(void) const
Returns the thread id of the instruction.
Definition: instruction.cpp:99
TRITON_EXPORT void removeReadImmediate(const triton::arch::Immediate &imm)
Removes a read immediate.
TRITON_EXPORT bool isBranch(void) const
Returns true if this instruction is a branch.
TRITON_EXPORT bool isPrefixed(void) const
Returns true if the instruction has a prefix (mainly for X86).
TRITON_EXPORT void setBranch(bool flag)
Sets flag to define this instruction as branch or not.
TRITON_EXPORT void setSize(triton::uint32 size)
Sets the size of the instruction.
TRITON_EXPORT Instruction()
Constructor.
Definition: instruction.cpp:19
TRITON_EXPORT void setCodeCondition(triton::arch::arm::condition_e codeCondition)
Sets the code condition of the instruction (mainly for AArch64).
TRITON_EXPORT std::set< std::pair< triton::arch::Register, triton::ast::SharedAbstractNode > > & getWrittenRegisters(void)
Returns the list of all implicit and explicit register (flags includes) outputs (write)
std::vector< triton::arch::OperandWrapper > operands
A list of operands.
bool tainted
True if this instruction is tainted. This field is set at the semantics level.
TRITON_EXPORT void removeWrittenRegister(const triton::arch::Register &reg)
Removes a written register.
std::set< triton::arch::Register > undefinedRegisters
Implicit and explicit undefined registers. This field is set at the semantics level.
Definition: instruction.hpp:90
TRITON_EXPORT void setReadImmediate(const triton::arch::Immediate &imm, const triton::ast::SharedAbstractNode &node)
Sets a read immediate.
std::set< std::pair< triton::arch::Register, triton::ast::SharedAbstractNode > > readRegisters
Implicit and explicit register inputs (read). This field is set at the semantics level.
Definition: instruction.hpp:81
TRITON_EXPORT void setControlFlow(bool flag)
Sets flag to define this instruction changes the control flow or not.
TRITON_EXPORT bool isUpdateFlag(void) const
Returns true if the instruction updates flags. Mainly used for AArch64 instructions like ADDS.
bool updateFlag
True if this instruction updartes flags. Mainly used for AArch64 instruction like ADDS.
TRITON_EXPORT triton::arch::x86::prefix_e getPrefix(void) const
Returns the prefix of the instruction (mainly for X86).
TRITON_EXPORT ~Instruction()
Destructor.
Definition: instruction.cpp:53
std::set< std::pair< triton::arch::Register, triton::ast::SharedAbstractNode > > writtenRegisters
Implicit and explicit register outputs (write). This field is set at the semantics level.
Definition: instruction.hpp:84
TRITON_EXPORT void setOpcode(const triton::uint8 *opcode, triton::uint32 size)
Sets the opcode of the instruction.
std::vector< triton::engines::symbolic::SharedSymbolicExpression > symbolicExpressions
The semantics set of the instruction.
TRITON_EXPORT std::set< std::pair< triton::arch::Immediate, triton::ast::SharedAbstractNode > > & getReadImmediates(void)
Returns the list of all implicit and explicit immediate inputs (read)
TRITON_EXPORT void setReadRegister(const triton::arch::Register &reg, const triton::ast::SharedAbstractNode &node)
Sets a read register.
TRITON_EXPORT const triton::engines::symbolic::SharedSymbolicExpression & addSymbolicExpression(const triton::engines::symbolic::SharedSymbolicExpression &expr)
Adds a symbolic expression.
triton::uint64 address
The address of the instruction.
Definition: instruction.hpp:54
TRITON_EXPORT void removeStoreAccess(const triton::arch::MemoryAccess &mem)
Removes a store access.
TRITON_EXPORT void setThreadId(triton::uint32 tid)
Sets the thread id of the instruction.
bool conditionTaken
True if the condition is taken (i.g x86: jcc, cmocc, setcc, ...). This field is set at the semantics ...
Definition: instruction.hpp:99
triton::uint32 tid
The thread id of the instruction.
Definition: instruction.hpp:51
TRITON_EXPORT triton::arch::arm::condition_e getCodeCondition(void) const
Returns the code codition of the instruction (mainly for AArch64).
TRITON_EXPORT std::string getDisassembly(void) const
Returns the disassembly of the instruction.
bool branch
True if this instruction is a branch. This field is set at the disassembly level.
Definition: instruction.hpp:93
TRITON_EXPORT triton::uint64 getNextAddress(void) const
Returns the next address of the instruction.
TRITON_EXPORT bool isControlFlow(void) const
Returns true if this instruction changes the control flow (e.g x86: JMP, JCC, CALL,...
This class is used to represent a memory access.
TRITON_EXPORT bool isOverlapWith(const MemoryAccess &other) const
Returns true if other and self overlap.
TRITON_EXPORT triton::uint64 getAddress(void) const
Returns the address of the memory.
This class is used as operand wrapper.
TRITON_EXPORT triton::arch::operand_e getType(void) const
Returns the abstract type of the operand.
TRITON_EXPORT const triton::arch::MemoryAccess & getConstMemory(void) const
Returns the memory operand as const.
TRITON_EXPORT const triton::arch::Register & getConstRegister(void) const
Returns the register operand.
TRITON_EXPORT const triton::arch::Immediate & getConstImmediate(void) const
Returns the immediate operand.
This class is used when an instruction has a register operand.
Definition: register.hpp:44
TRITON_EXPORT triton::arch::register_e getId(void) const
Returns the id of the register.
Definition: register.cpp:53
TRITON_EXPORT bool isOverlapWith(const Register &other) const
Returns true if other and self overlap.
Definition: register.cpp:83
The exception class used by an instruction.
Definition: exceptions.hpp:269
std::ostream & operator<<(std::ostream &stream, const BitsVector &bv)
Displays a BitsVector.
Definition: bitsVector.cpp:103
@ OP_IMM
immediate operand
Definition: archEnums.hpp:49
@ OP_MEM
memory operand
Definition: archEnums.hpp:50
@ OP_REG
register operand
Definition: archEnums.hpp:51
condition_e
Types of condition.
Definition: archEnums.hpp:144
@ ID_CONDITION_INVALID
invalid
Definition: archEnums.hpp:145
std::shared_ptr< triton::ast::AbstractNode > SharedAbstractNode
Shared Abstract Node.
Definition: ast.hpp:57
constexpr triton::uint32 flag
flag size in bit
Definition: cpuSize.hpp:56
std::shared_ptr< triton::engines::symbolic::SymbolicExpression > SharedSymbolicExpression
Shared Symbolic Expression.
Definition: ast.hpp:38
std::uint64_t uint64
unisgned 64-bits
Definition: tritonTypes.hpp:34
std::uint32_t uint32
unisgned 32-bits
Definition: tritonTypes.hpp:31
std::uint8_t uint8
unisgned 8-bits
Definition: tritonTypes.hpp:25
prefix_e
Types of prefix.
Definition: archEnums.hpp:91
@ ID_PREFIX_INVALID
invalid
Definition: archEnums.hpp:92
The Triton namespace.
Definition: api.cpp:227